1. Field of the Invention
This invention relates to data processing systems. More particularly, this invention relates to data processing systems having memory protection units.
2. Description of the Prior Art
It is known to control memory access in data processing systems using memory protection units. These memory protection units define a plurality of protection regions whose properties are configured by writing to protection unit registers. This provides a level of control over memory properties and enables different memory regions with different attributes to be specified. Memory protection units are similar to memory management units, but are simpler in the sense that they do not involve mapping of virtual to physical addresses. Furthermore, memory protection units do not use translation tables, but limit themselves to a relatively small number of regions in hardware to improve the predicatability of response.
It is also known to program memory protection units to have two or more overlapping memory regions. Overlapping regions increase the flexibility of how the memory regions can be mapped onto physical memory devices in the data processing system. However, in order to simplify the implementation cost there are usually certain constraints on the way that memory regions can be allocated. The size of a memory region must be a power of two and can range, for example, from 250 B up to 4 GB. However, the starting address of the memory region is constrained to be multiple of the region size, that is, for a region of size 2n the starting address must be k*2n where k is an integer. This means that it is not possible in such systems to define memory regions of arbitrary size. Although, systems having arbitrary sized memory regions can be built, it is much more expensive to do so. Memory protection units typically offer in the range of eight to sixteen different memory regions.
Due to the constraint on the way that memory regions are allocated in known systems it may be necessary to allocate more than one memory region with a respective set of memory attributes to define a memory block of a given size as required by a processing apparatus. This is because the memory attributes must be applied to the entire memory region.
Furthermore, the delineation of memory regions by known memory protection units is particularly inflexible in situations where application processes running on the data processing apparatus require access permission to different groups of peripheral devices. This difficulty arises from the situation that typically a contiguous block of memory will be allocated to a full set of peripheral devices. Due to the diverse nature of different application processes executed by the data processing apparatus, it is normal that different processes will require different sets of access permissions to different sub-sets of the peripheral devices in known memory units. To accommodate this situation, it is known to allocate to each individual peripheral device, a respective memory region. Since typically only eight to sixteen memory regions are provided, the demands from the limited number of regions are high and this has lead to a requirement for an increasing number of memory regions to be defined by the memory protection unit. Thus there is a need for a data processing apparatus that offers more flexibility than known memory protection units yet does not involve the overheads of introducing increasing large numbers of memory protection regions.